1. Field of the Invention
The present invention relates to a semiconductor device structure and a method of manufacturing the same. In particular, the invention relates to a semiconductor device structure incorporating a plurality of element isolation insulating films having different depths, as well as a method of manufacturing the same.
2. Description of the Background Art
An SOI (Silicon On Insulator) substrate is of a stacked structure in which a silicon substrate (hereinafter also called xe2x80x9csemiconductor substratexe2x80x9d), a buried oxide film (hereinafter also called xe2x80x9cBOX layerxe2x80x9d or xe2x80x9cinsulating layerxe2x80x9d), and a silicon layer (hereinafter also called xe2x80x9csemiconductor layerxe2x80x9d) are stacked in the order named. Heretofore, the main semiconductor device using an SOI substrate was of the type in which semiconductor elements are surrounded by a full shallow trench isolation (FTI) extending from the upper surface of a semiconductor layer to the upper surface of an insulating layer. The semiconductor device of this type has, as compared to that using a bulk substrate not an SOI substrate, the following advantages: (i) no latch up occurs even with the formation of CMOS transistors; (ii) junction capacitance can be lowered to realize high speed operation; and (iii) the leakage current during standby condition is lessened to reduce power consumption.
However, the semiconductor device of this type has had various problems due to the semiconductor layer being in an electrically floating state, as follows. Firstly, kink effect may occur in IDS-VDS characteristics, or an operational breakdown voltage may be lowered, because the carrier generated by impact ionization is stored in a lower part of a channel formation region. Secondly, the frequency dependence of a drain conductance (g0) may occur because of an unstable potential of the channel formation region. Thirdly, the dependency to switching history may occur in the gate delay time because of an unstable potential of the channel formation region.
To overcome these problems, Japanese Patent Application Laid-Open No. 58-124243 (1983) has proposed a semiconductor device of the type in which a body contact region is selectively formed in an upper surface of a semiconductor layer, and semiconductor elements are surrounded by a partial shallow trench isolation (PTI) extending from the upper surface of the semiconductor layer to such a depth as not to reach the upper surface of an insulating layer. In the semiconductor device of this type, the body contact region and a channel formation region are electrically connected with each other, through the semiconductor layer disposed between the bottom surface of the PTI and the upper surface of the insulating layer. Therefore, the potential of the channel formation region can be fixed by an external power supply connected to the body contact region.
Recently, in order to achieve the scale down of semiconductor devices, there has been proposed a semiconductor device of the type which collectively fixes the potentials of the channel formation regions of a plurality of transistors of the same conductivity type, without individually fixing the potential of a channel formation region per transistor (see Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp140, 141, 164, 165, 170 and 171). In the semiconductor device of this type, the respective channel formation regions of adjacent transistors are isolated from each other, by a PTI.
Conventional Technique I
One example of the last-mentioned type semiconductor device will be described hereinafter. FIG. 28 is a top plan view of a semiconductor device structure according to a conventional technique I, and FIGS. 29 and 30 are sectional views taken along line L101 and line L102, respectively, in the semiconductor device shown in FIG. 28. For the sake of convenience, interlayer insulating films 127 to 129 shown in FIGS. 29 and 30, are omitted in FIG. 28. Referring to FIGS. 28 to 30, the semiconductor device of the conventional technique I comprises a PTI 140 disposed in a PTI formation region 101; a source/drain region 103 having a high concentration impurity region 118 and low concentration impurity region 119; a channel formation region 104 (i.e., a P type channel formation region 104n and an N type channel formation region 104p); source/drain wirings 105a and 105b; a gate wiring 106 having a stacked structure in which a doped polysilicon layer 121 and metal layer 122 are stacked in the order named; metal wirings 107 and 111; contact holes 108, 110, 125a and 125b; a body contact region 109; an SOI substrate 114 having a silicon substrate 115, BOX layer 116 and silicon layer 117; a gate oxide film 120; an insulating film 123; a sidewall 124; interlayer insulating films 127 to 129; a P type channel stopper layer 125; and an N type channel stopper layer 126.
Referring to FIG. 29, the NMOS and PMOS disposed adjacent each other are isolated by a PTI 140a. In the portion of the silicon layer 117 which is sandwiched between the bottom surface of the PTI 140a and the upper surface of the BOX layer 116, the N type channel stopper layer 126 is disposed on the side on which a PMOS formation region is disposed, and the P type channel stopper layer 125 is disposed on the side on which an NMOS formation region is disposed.
Referring to FIG. 30, an N+ type body contact region 109 and an N type channel formation region 104p are electrically connected together, through an N type channel stopper layer 126 disposed in the portion of the silicon layer 117 which is sandwiched between the bottom surface of the PTI 140 and the upper surface of a BOX layer 116. Therefore, the potential of the channel formation region 104p can be fixed to the potential of a metal wiring 111 which is electrically connected to the body contact region 109, via the contact hole 110 filled with a conductive plug.
Conventional Technique II-a
Other conventional semiconductor device structure using a bulk substrate will be described hereinafter. FIG. 31 is a top plan view of a semiconductor device structure according to a conventional technique II-a, and FIG. 32 is a sectional view taken along line L103 in the semiconductor device shown in FIG. 31. For the sake of simplicity, only the internal structure of a silicon substrate 160 is illustrated in FIG. 32. Referring to FIGS. 31 and 32, the semiconductor device of the conventional technique II-a comprises a silicon substrate 160; an STI (Shallow Trench Isolation) 163 disposed in an element isolation region 150; a channel stopper layer 162; a bottom N well 164 disposed only in a memory cell region of the silicon substrate 160; a P well 161 overlying the bottom N well 164 and extending across the entire surface of the silicon substrate 160; a source/drain region 165; a channel formation region 166; a plurality of memory cells 151 disposed in the memory cell region of the silicon substrate 160; a plurality of NMOSs which have a source/drain region 154 and a gate electrode 155 and are disposed in a peripheral circuit region of the silicon substrate 160 on which a sense amplifier, etc. are disposed; a plurality of bit lines 152; and a plurality of word lines 153. The bottom N well 164 is provided for improving the soft error tolerance of the memory cells 151.
Referring to FIG. 32, the memory cell region and peripheral circuit region of the silicon substrate 160 are isolated by an STI 163a which is formed in such a depth as to extend from the upper surface of the silicon substrate 160 to the upper surface of the channel stopper layer 162. An STI 163 having the same depth as the STI 163a is disposed in the memory cell region and peripheral circuit region of the silicon substrate 160, respectively.
Conventional Technique II-b
A modification of the semiconductor device according to the conventional technique II-a will be described hereafter. FIG. 33 is a top plan view of a semiconductor device structure according to a conventional technique II-b, and FIG. 34 is a sectional view taken along the line L104 in the semiconductor device shown in FIG. 33. For the sake of simplicity, only the internal structure of a silicon substrate 160 is illustrated in FIG. 34. Referring to FIGS. 33 and 34, the semiconductor device of the conventional technique II-b comprises a silicon substrate 160; an STI 163 disposed in an element isolation region 150; a channel stopper layer 162; bottom N wells 164 disposed in a memory cell region and peripheral circuit region of the silicon substrate 160; a P well 161 a disposed on the bottom N well 164 in the memory cell region of the silicon substrate 160; an N well 161b formed in the peripheral circuit region of the silicon substrate 160 so as to be shallower than the N well 161a; a source/drain region 165; a channel formation region 166; a plurality of memory cells 151 disposed in the memory cell region of the silicon substrate 160; a plurality of NMOSs which have a source/drain region 154 and a gate electrode 155 and are disposed in the peripheral circuit region of the silicon substrate 160; a plurality of bit lines 152; and a plurality of word lines 153. By making the P well 161b of the peripheral circuit region shallower than the P well 161a of the memory cell region, the breakdown voltage between the wells can be increased and the leakage current between the wells can be lowered in the peripheral circuit region. Thereby, in the peripheral circuit region, the width of an element isolation insulating film (not shown) for effecting isolation between the adjacent wells can be reduced, thus leading to the chip area reduction.
Referring to FIG. 34, the memory cell region and peripheral circuit region of the silicon substrate 160 are, as shown in FIG. 32, isolated by an STI 163a which is formed in such a depth as to extend from the upper surface of the silicon substrate 160 to the upper surface of the channel stopper layer 162. Also, as shown in FIG. 32, an STI 163 having the same depth as the STI 163a is disposed in the memory cell region and peripheral circuit region of the silicon substrate 160, respectively.
These conventional semiconductor devices, however, have the following drawbacks.
Drawbacks of Conventional Technique I
Referring again to FIG. 29, two drawbacks of the conventional technique I will be described as follows. Firstly, consider the case of applying 0 V to a metal wiring 105bp and a power supply voltage VDD to a metal wiring 105an, in such a state that a substrate voltage VBB is applied to the channel stopper layer 125 and to the channel formation region 104n, and a power supply voltage VDD is applied to the channel stopper layer 126 and to the channel formation region 104p. Due to the potential difference between the metal wiring 105bp and metal wiring 105an, a leakage current flows, via the channel stopper layers 125 and 126 underlying the PTI 140a, between the source/drain region 103 of the PMOS and the source/drain region 103 of the NMOS which are oppositely disposed and sandwich therebetween the PTI 140a. In general, PTIs have a lower element isolation breakdown voltage than FTIs. Therefore, in order to prevent such an occurrence, it is necessary to increase the width W101 of the PTI 140a between the PMOS and NMOS. This constitutes an obstruction to the scale down of semiconductor devices.
Secondly, referring again to FIG. 29, in the NMOS formation region, the P type channel stopper layer 125 underlying the PTI 140 forms a PN junction with the N type source/drain region 103. In the PMOS formation region, the N type channel stopper layer 126 underlying the PTI 140 forms a PN junction with the P type source/drain region 103. By the presence of these PN junctions, the junction capacitance is increased so that the delay time of the transistor switching operation is increased and the circuit operation is retarded.
Drawbacks of Conventional Technique II-a
FIG. 35 is a schematic sectional view of an ion implantation for forming a bottom N well 164. FIG. 36 is a sectional view showing in enlarged dimension the region X in FIG. 35. Referring to FIG. 35, with the vicinity of the center of an STI 163a as an alignment position, a photoresist 171 having a thickness of about 3 to 6 xcexcm is formed on a peripheral circuit region of a silicon substrate 160, by means of a photolithographic process. By using the photoresist 171 as mask, phosphorus ions 170 is implanted into the silicon substrate 160 to form a bottom N well 164.
At this time, it is desirable that the edge of the photoresist 171 be perpendicular to the substrate surface. In fact, however, a taper 172 inclined toward the plane of the substrate surface at an angle of about 80xc2x0 to 87xc2x0, is formed on the side surface of the photoresist 171. As a result, the phosphorus ions 170 are implanted into the portion of the silicon substrate 160 which is nearer to the peripheral circuit region than the alignment position. Thereby, lifted portions 164a and 164b of the N well 164, which follow the contours of the outer surface of the taper 172, are formed in the silicon substrate 160 underlying the STI 163a. Although the lifted portions 164a and 164b are originally connected together, these are separated because the concentration of the P type impurity is higher than that of the N type impurity, in the vicinity of the middle of the P well 161. Thereby, the lifted portion 164b is formed as a layer isolated from the bottom N well 164.
Referring to FIG. 36, when an N type source/drain region 165 of a memory cell region and an N type source/drain region 154 of a peripheral circuit region are isolated from each other by an STI 163a, a large leakage current will flow between the source/drain regions 165 and 154, depending on the bias conditions, which can cause malfunction. That is, a leakage current is caused by the lifted portions 164a and 164b of the bottom N well 164. The leakage current flows through the following two paths: a path 175 extending from the source/drain region 154 via the lifted portion 164a to the bottom N well 164; and a path 176 extending from the source/drain region 154 via the lifted portion 164b to the source/drain region 165. The reason why a leakage current flows is that, via the lifted portions 164a and 164b, the depletion layers of the source/drain regions 165 and 154 are connected with the depletion layer of the bottom N well 164, respectively.
In order to avoid such a leakage current, it is therefore necessary to increase the width W104 of the STI 163a between the memory cell region and peripheral circuit region, thus constituting an obstruction to the scale down of semiconductor devices.
Drawbacks in Conventional Technique II-b
FIG. 37 is a schematic sectional view of an ion implantation for forming a P well 161a. FIG. 38 is a sectional view showing in enlarged dimension the region Y in FIG. 37. Referring to FIGS. 37 and 38, a bottom N well 164 is formed on the entire surface of a wafer across a memory cell region and a peripheral circuit region of a silicon substrate 160. With the vicinity of the center of an STI 163a as an alignment position, a photoresist 181 having a thickness of about 3 to 6 xcexcm is formed on the peripheral circuit region of the silicon substrate 160 by means of a photolithographic process. By using the photoresist 181 as a mask, boron ions 180 are implanted into the silicon substrate 160 to form a P well 161a. At this time, a taper 182 is formed on the side surface of the photoresist 181, and a P well lifted portion 161c which follows the contours of the outer surface of the taper 182 is formed in the silicon substrate 160 underlying the STI 163a, as previously described.
The P well lifted portion 161c derived from the P well 161a of the memory cell region extends into a channel formation region 166 of an NMOS in the peripheral circuit region. Therefore, the minority carriers (electrons) created in the peripheral circuit region, which serve as a leakage current, pass through the P well lifted portion 161c and the P well 161a to the memory cell region, thereby breaking the data stored in the memory cell.
In order to avoid occurrence of such a leakage current, it is therefore necessary to increase width W105 of the STI 163a between the memory cell region and peripheral circuit region, thereby constituting an obstruction to the scale down of semiconductor devices.
The foregoing description was made on the assumption that the sense amplifier of the peripheral circuit region is formed by the NMOS. However, a similar problem can occur even if the sense amplifier is formed by a PMOS or CMOS. Also, a similar problem can occur when the memory cell at the end of the memory cell region, which is adjacent via the STI 163a to the peripheral circuit region, is a dummy cell.
According to a first aspect of the present invention, a semiconductor device comprises: an SOI substrate having a stacked structure in which a semiconductor substrate, insulating layer and semiconductor layer are stacked in the order named; a first MOS transistor having a first channel formation region of a first conductivity type selectively formed in a main surface of the semiconductor layer; a second MOS transistor adjacent to the first MOS transistor, having a second channel formation region of a second conductivity type different from the first conductivity type and being selectively formed in the main surface of the semiconductor layer; first and second body contact regions selectively formed in the main surface of the semiconductor layer; a first element isolation insulating film of a partial isolation type disposed between the first body contact region and the first channel formation region, having such a depth as to extend from the main surface of the semiconductor layer and not reaching an upper surface of the insulating layer; a second element isolation insulating film of the partial isolation type disposed between the second body contact region and the second channel formation region, having such a depth as to extend from the main surface of the semiconductor layer and not reaching the upper surface of the insulating layer; and a third element isolation insulating film of a full isolation type extending from the main surface of the semiconductor layer to the upper surface of the insulating layer, disposed in a region containing at least the space between the first and second MOS transistors.
According to a second aspect, the semiconductor device of the first aspect is characterized in that the first MOS transistor further has paired source/drain regions of the second conductivity type sandwiching therebetween the first channel formation region and being selectively formed in the main surface of the semiconductor layer; and that the third element isolation insulating film surrounds the first MOS transistor, except for at least one of two side surfaces of the first channel formation region making no contact with the source/drain regions.
According to a third aspect the semiconductor device of the second aspect is characterized in that the third element isolation film surrounds the first MOS transistor, except for the two side surfaces of the first channel formation region; and that the first element isolation insulating film is formed in the space between the first body contact region and the two side surfaces of the first channel formation region.
According to a fourth aspect, the semiconductor device of the second or third aspect is characterized in that the first MOS transistor further has a gate electrode disposed on the main surface of the semiconductor layer above the first channel formation region; that the semiconductor device further comprises a channel stopper layer of the first conductivity type disposed in the portion of the semiconductor layer which is sandwiched between a bottom surface of the first element isolation insulating film and the upper surface of the insulating layer; and that the channel stopper layer has such a high impurity concentration as to satisfy {square root over ((CBxc2x7RB))} less than tgate, wherein CB and RB are the capacitance and resistance between the first channel formation region and the first body contact region, respectively, and tgate is a signal transition time of a pulse signal applied to the gate electrode.
According to a fifth aspect, a semiconductor device comprises: an SOI substrate having a stacked structure in which a semiconductor substrate, insulating layer and semiconductor layer are stacked in the order named; a first element isolation insulating film of a partial isolation type selectively formed in a memory cell region of the SOI substrate at a first depth extending from a main surface of the semiconductor layer and not reaching an upper surface of the insulating layer; a second element isolation insulating film of the partial isolation type selectively formed in a peripheral circuit region of the SOI substrate isolated from the memory cell region by an element isolation region of the SOI substrate, at a second depth extending from the main surface of the semiconductor layer and not reaching the upper surface of the insulating layer; and a third element isolation insulating film formed deeper than the first and second depth from the main surface of the semiconductor layer in the element isolation region.
According to a sixth aspect, the semiconductor device of the fifth aspect is characterized in that the third element isolation insulating film is an element isolation insulating film of a full isolation type extending from the main surface of the semiconductor layer and reaching the upper surface of the insulating layer.
According to a seventh aspect, a semiconductor device comprises: a substrate having first and second regions isolated by an element isolation region, a first element isolation insulating film selectively formed at a first depth in a main surface of the substrate in the first region of the substrate; a second element isolation insulating film selectively formed at a second depth in the main surface of the substrate in the second region of the substrate; an impurity introducing region disposed within the substrate only in the first region of the first and second regions of the substrate by performing an ion implantation into the substrate; and a third element isolation insulating film formed in the element isolation region of the substrate so as to extend from the main surface of the substrate to a point deeper than at least the first or second depth.
According to an eighth aspect, the semiconductor device of the seventh aspect is characterized in that the impurity introducing region is a first well of a first conductivity type; that the semiconductor device further comprises in the substrate a second well of a second conductivity type different from the first conductivity type, disposed on the first well across the first and second regions; and that the third element isolation insulating film extending from the main surface of the substrate to a point deeper than at least an upper surface of the second well.
According to a ninth aspect, the semiconductor device of the eighth aspect is characterized in that the third element isolation insulating film extends from the main surface of the substrate and reaches a bottom surface of the second well.
According to a tenth aspect, the semiconductor device of the seventh aspect is characterized in that the impurity introducing region is a first well of a first conductivity type; that the semiconductor device further comprises a second well of a second conductivity type different from the first conductivity type, disposed beneath the first well across the first and second regions; and that the third element isolation insulating film extends from the main surface of the substrate and reaches a bottom surface of the first well.
According to an eleventh aspect, a method of manufacturing a semiconductor device comprises the steps of: (a) preparing a substrate; (b) forming a first recess of a first depth by digging a first portion of a main surface of the substrate; (c) forming a predetermined film on a bottom surface of the first recess; (d) forming a second recess of a second depth shallower than the first depth by digging a second portion of the main surface of the substrate while the first recess is used to protect the main surface of the substrate underlying the first recess, which step is performed after the step (c); (e) removing the predetermined film, which step is performed after the step (d); and (f) filling the first and second recesses with an insulating film, which step is performed after the step (e).
With the first aspect, the first and second MOS transistors which are adjacent each other and have different conductivity types are isolated by the third element isolation insulating film of the full isolation. Therefore, as compared with an element isolation insulating film of a partial isolation, the width of the element isolation insulating film can be made shorter, thereby permitting the scale down of semiconductor devices.
In addition, the potentials of the first and second channel formation regions can be fixed because an electrical connection between the first body contact region and first channel formation region, and that between the second body contact region and second channel formation region, are made through the portion of the semiconductor layer which is sandwiched between the bottom surface of the first or second element isolation insulating film of the partial isolation type and the upper surface of the insulating layer.
With the second aspect, the source/drain region is surrounded by the third element isolation insulating film of the full isolation type, except for at least one of the two side surfaces of the first channel formation region. Therefore, when the channel stopper layer of the first conductivity type underlies the first element isolation insulating film of the partial isolation type, the junction capacitance generated between the channel stopper layer and source/drain regions can be lowered, thus permitting a high speed operation of semiconductor devices.
In addition, a small contact area between the channel stopper layer and source/drain regions enables to set the impurity concentration of the channel stopper layer at a high concentration.
With the third aspect, a uniform potential distribution in the direction in which the first channel formation region extends can be obtained because the potential of the first channel formation region can be fixed from both side surfaces.
With the fourth aspect, by increasing the impurity concentration of the channel stopper layer, the value of RB can be lowered and the potential of the first channel formation region can be fixed stably.
With the fifth aspect, the element isolation breakdown voltage of the third element isolation insulating film is higher than that of the first or second element isolation insulating film. This allows for a reduction in the width of the third element isolation insulating film, thus permitting the scale down of semiconductor devices.
With the sixth aspect, the element isolation breakdown voltage of the third element isolation insulating film can be further increased. This allows for a further reduction in the width of the third element isolation insulating film, thus enhancing the scale down of semiconductor devices.
With the seventh aspect, even when the lifted portion of the impurity introducing region is formed in the second region of the substrate due to the taper shape of the photoresist used in ion implantation, at least part of the lifted portion can be absorbed by the third element isolation insulating film, by forming the third element isolation insulating film deeper than the first or second element isolation insulating film.
With the eighth aspect, the lifted portion formed in the vicinity of the upper surface of the second well can be absorbed by the third element isolation insulating film.
With the ninth aspect, the lifted portion formed in the vicinity of the bottom surface of the second well can be absorbed by the third element isolation insulating film.
In addition, since the second well is divided by the third element isolation insulating film, the potential of the second well in the first region and that in the second region can be set independently.
With the tenth aspect, all the minority carriers created in the first or second region can be captured by the second well. Thus, it is avoided that the minority carriers diffuse from the first or second region to the second or first region.
In addition, since the first well is divided by the third element isolation insulating film, the potential of the first well in the first region and that in the second region can be set independently.
With the eleventh aspect, a plurality of element isolation insulating films having different depths can be formed in the main surface of the substrate by filling the first and second recesses having different depths, with an insulating film.
It is therefore a major object of the present invention to provide a semiconductor device structure and a manufacturing method thereof with which the scale down of a semiconductor device, especially, a semiconductor device using an SOI substrate, can be realized by suppressing a leakage current and decreasing a junction capacitance with the potential of a channel formation region fixed.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.